The present invention relates generally to integrated circuit designs, and more particularly to a system for discharging bit-lines of memory designs before for triggering a data storage to increase read speed.
Various types of memory devices are widely used in computing devices today. There are Read-only memory (ROM) devices as well as Read-Access memory (RAM) devices. ROM is typically used as a storage medium in computer devices. Since it cannot easily be written to, its main uses lie in the distribution of firmware, or software that is both very closely related to hardware and not likely to need frequent upgrading.
Conventional methods used for sensing the states of memory cells utilize a sense amplifier along with a latch. The sense amplifier senses the voltage from the charged bit-line to determine the state of a memory cell as the charged bit-line leaks to certain voltage levels that are predetermined for high and low states of memory cells. However, the time margin required for the charged bit-line to leak to the predetermined high state voltage level and low state voltage level can vary. Since the voltage level for a high state memory cell is much higher than the voltage level used for determining the low state memory cell, the time margin required for voltage to leak to voltage level of a low state memory cell is typically much higher. The read margin may suffer due to the large time margin required for voltage to leak to the predetermined voltage levels. Not having enough read margin can affect the yield and create reliability issues. Read access time for current ROM circuit design is also slow since bit-lines are never discharged before latching. This creates extra time delay slowing down the read process.
It is therefore desirable to have an improved circuit design that can provide reliable state detection without as much time delay.